Bogdan Pasca's research topics

Bogdan Pasca
PERSONAL WEBPAGE

Research

Bogdan Pasca
Hybrid Dot-Product Design for FP-Enabled FPGAs
2019 IEEE 26nd Symposium on Computer Arithmetic (ARITH)
[bibtex] [pdf]

@INPROCEEDINGS{Pasca2019:ARITH,
author={B. {Pasca}},
booktitle={2019 IEEE 26th Symposium on Computer Arithmetic (ARITH)},
title={Hybrid Dot-Product Design for {FP}-Enabled {FPGAs}},
year={2019},
volume={},
number={},
pages={194-196},
keywords={field programmable gate arrays;floating point arithmetic;logic design;matrix multiplication;multiplying circuits;neural nets;matrix-matrix multiply engines;matrix multiplication;single-precision arithmetic;hybrid dot-product design;neural network training;dot-products;FP-enabled FPGA;hybrid dot-product implementation;Field programmable gate arrays;Adders;Lead;Training;Neural networks;Tools;Bandwidth;hybrid;dot product;FPGA;arithmetic;floating point;bfloat16;single precision;generator},
doi={10.1109/ARITH.2019.00045},
ISSN={1063-6889},
month={June},}

E. Nurvitadhi and D. Kwon and A. Jafari and A. Boutros and J. Sim and P. Tomson and H. Sumbul and G. Chen and P. Knag and R. Kumar and R. Krishnamurthy and S. Gribok and B. Pasca and M. Langhammer and D. Marr and A. Dasu
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs
2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
[bibtex] [pdf]

@INPROCEEDINGS{RNN2019:FCCM,
  author={E. {Nurvitadhi} and D. {Kwon} and A. {Jafari} and A. {Boutros} and J. {Sim} and P. {Tomson} and H. {Sumbul} and G. {Chen} and P. {Knag} and R. {Kumar} and R. {Krishnamurthy} and S. {Gribok} and B. {Pasca} and M. {Langhammer} and D. {Marr} and A. {Dasu}},
  booktitle={2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
  title={Why Compete When You Can Work Together: {FPGA-ASIC} Integration for Persistent {RNNs}},
  year={2019},
  volume={},
  number={},
  pages={199-207},
  keywords={application specific integrated circuits;computer centres;field programmable gate arrays;graphics processing units;learning (artificial intelligence);recurrent neural nets;FPGA-ASIC integration;interactive intelligent services;smart web search;dataintensive deep learning algorithms;off-chip memory accesses;Nvidia's cuDNN libraries;GPU;Nvidia Volta;ASIC chiplet;INT8;datacenter workloads;RNN;Microsoft's Brainwave;LSTM;TensorRAM;system-in-package;Field programmable gate arrays;System-on-chip;Graphics processing units;Computational modeling;Real-time systems;Hazards;Throughput;Deep learning;system in package;fpga;chiplet;persistent AI},
  doi={10.1109/FCCM.2019.00035},
  ISSN={2576-2613},
month={April},}

Martin Langhammer, Bogdan Pasca and Gregg Baeckler
High Precision, High Performance FPGA Adders
2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
[bibtex] [pdf]

@INPROCEEDINGS{LanghammerPascaBaeckler2019:FCCM, 
  author={M. Langhammer and B. Pasca and G. Baeckler}, 
  booktitle={2019 {IEEE} 27th {A}nnual {I}nternational {S}ymposium on {F}ield-{P}rogrammable {C}ustom {C}omputing {M}achines {(FCCM)}}, 
  title={High Precision, High Performance {FPGA} Adders},
  year={2019},
  volume={},
  number={},
  pages={298-306},
  keywords={adders;computer centres;digital arithmetic;field programmable gate arrays;integrated circuit layout;logic design;network routing;public key cryptography;high-performance integer adders;many-core chip-filling   configurations;chip-filling designs;adder function;high performance FPGA adders;smart Network Interface Cards;public key cryptography algorithms;floor-planned nonarithmetic applications;Adders;Field programmable gate arrays;Routing;Pipeline processing;Performance evaluation;Pipelines;Computer architecture;FPGA;adder;wide;prefix},
  doi={10.1109/FCCM.2019.00047},
  ISSN={2576-2613},
  month={April},
}

Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil V. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Aravind Dasu
Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI
2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
[bibtex]

@inproceedings{DBLP:conf/fpga/NurvitadhiKJBST19,
  author    = {Eriko Nurvitadhi and
               Dongup Kwon and
               Ali Jafari and
               Andrew Boutros and
               Jaewoong Sim and
               Phillip Tomson and
               Huseyin Sumbul and
               Gregory K. Chen and
               Phil V. Knag and
               Raghavan Kumar and
               Ram Krishnamurthy and
               Debbie Marr and
               Sergey Gribok and
               Bogdan Pasca and
               Martin Langhammer and
               Aravind Dasu},
  title     = {Evaluating and Enhancing Intel{\textregistered} Stratix{\textregistered}
               10 FPGAs for Persistent Real-Time {AI}},
  booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
               Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
  pages     = {119},
  year      = {2019},
  crossref  = {DBLP:conf/fpga/2019},
  url       = {https://doi.org/10.1145/3289602.3293943},
  doi       = {10.1145/3289602.3293943},
  timestamp = {Tue, 05 Mar 2019 07:04:43 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/fpga/NurvitadhiKJBST19},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

Martin Langhammer and Bogdan Pasca Gregg Baeckler and Sergey Gribok
Extracting INT8 Multipliers from INT18 Multipliers
2019 29th International Conference on Field Programmable Logic and Applications (FPL)
[bibtex] [pdf]

@INPROCEEDINGS{LanghammerPascaBaecklerGribok2019:FPL,
  author={M. {Langhammer} and B. {Pasca} and G. {Baeckler} and S. {Gribok}},
  booktitle={2019 29th {I}nternational {C}onference on {F}ield {P}rogrammable {L}ogic and {A}pplications {(FPL)}},
  title={Extracting {INT8} Multipliers from {INT18} Multipliers},
  year={2019},
  volume={},
  number={},
  pages={114-120},
  keywords={Field programmable gate arrays;Logic gates;Adders;Artificial intelligence;US Department of Transportation;Routing;Computer architecture;FPGA;multiplication;DSP;int8;int18;extraction},
  doi={10.1109/FPL.2019.00027},
  ISSN={1946-147X},
  month={Sep.},
}

Martin Langhammer and Bogdan Pasca
High-Performance QR Decomposition for FPGAs
International Symposium on Field-Programmable Gate Arrays, {FPGA} 2018
Monterey, CA, USA, February 25-27, 2018
[bibtex] [pdf]

@inproceedings{LanghammerPasca2018:FPGA,
  author    = {Martin Langhammer and Bogdan Pasca},
  title     = {High-Performance {QR} Decomposition for {FPGAs}},
  booktitle = {Proceedings of the 2018 {ACM/SIGDA} International Symposium on Field-Programmable Gate Arrays, {FPGA} 2018, Monterey, CA, USA, February 25-27, 2018},
  pages     = {183--188},
  year      = {2018},
  crossref  = {DBLP:conf/fpga/2018},
  url       = {https://doi.org/10.1145/3174243.3174273},
  doi       = {10.1145/3174243.3174273},
  timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/fpga/LanghammerP18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

Martin Langhammer and Bogdan Pasca
Design and Implementation of an Embedded FPGA Floating Point DSP Block
Computer Arithmetic (ARITH), 2015 IEEE 22nd Symposium on
[bibtex] [pdf]

@INPROCEEDINGS{7203792, 
  author={M. Langhammer and B. Pasca}, 
  booktitle={Computer Arithmetic (ARITH), 2015 IEEE 22nd Symposium on}, 
  title={Design and Implementation of an Embedded FPGA Floating Point DSP Block}, 
  year={2015}, 
  pages={26-33}, 
  keywords={adders;digital signal processing chips;field programmable gate arrays;floating point arithmetic;logic design;reconfigurable architectures;ASIC;FPGA routing density;SP FP adder-subtracter;SP FP multiplier;circuit design;embedded FPGA floating point DSP block;embedded memory blocks;hardened DSP resources;low latency structure;multiply-add-based fixed-point arithmetic cores;power consumption penalty;single precision floating-point arithmetic;size 20 nm;soft logic resources;Adders;Digital signal processing;Field programmable gate arrays;Multiplexing;Pipelines;Registers;Routing;CPA;DSP;FPGA;floating-point;single precision;subnormal}, 
  doi={10.1109/ARITH.2015.18}, 
  ISSN={1063-6889}, 
  month={June},
}

Martin Langhammer and Bogdan Pasca
Activation Function Architectures for FPGAs
2018 28th International Conference on Field Programmable Logic and Applications (FPL)
[bibtex] [pdf]

@INPROCEEDINGS{LanghammerPasca2018:FPL, 
booktitle={2018 28th {I}nternational {C}onference on {F}ield {P}rogrammable {L}ogic and {A}pplications {(FPL)}},
title={Activation Function Architectures for {FPGAs}},
author={M. {Langhammer} and B. {Pasca}},
year={2018},
volume={},
number={},
pages={43-437},
keywords={electronic engineering computing;field programmable gate arrays;floating point arithmetic;learning (artificial intelligence);recurrent neural nets;activation function architectures;nonlinear activation functions;activation function quality;IEEE754 single precision hard floating point blocks;tanh function;FPGA;recurrent neural network topologies;IEEE754 FP32 single precision floating-point representations;integer arithmetic;IEEE754-2008 FP16 half precision floating-point representations;machine learning;Computer architecture;Field programmable gate arrays;Recurrent neural networks;Adders;Additives;Approximation error;FPGA;activation functions;hyperbolic tangent;sigmoid;machine learning},
doi={10.1109/FPL.2018.00015},
ISSN={1946-147X},
month={Aug},
}

Martin Langhammer and Bogdan Pasca
Single Precision Logarithm and Exponential Architectures for Hard Floating-Point Enabled FPGAs
IEEE Transactions on Computers ( Volume: 66 , Issue: 12 , Dec. 1 2017 ), Page(s): 2031 - 2043
[bibtex] [pdf]

@INPROCEEDINGS{LanghammerPasca2017:TC, 
author={M. {Langhammer} and B. {Pasca}},
journal={{IEEE} {T}ransactions on {C}omputers},
title={Single Precision Logarithm and Exponential Architectures for Hard Floating-Point Enabled {FPGAs}},
year={2017},
volume={66},
number={12},
pages={2031-2043},
keywords={Field programmable gate arrays;Digital signal processing;Computer architecture;Performance evaluation;Natural logarithm;exponential;floating-point;single-precision;FPGA;FP DSP Block;Arria 10;Stratix 10},
doi={10.1109/TC.2017.2703923},
ISSN={2326-3814},
month={Dec},}
}

Martin Langhammer and Bogdan Pasca
Floating Point Tangent Implementation for FPGAs
2017 IEEE 24th Symposium on Computer Arithmetic (ARITH)
London, UK
[bibtex] [pdf]

@INPROCEEDINGS{LanghammerPasca2017:ARITH, 
author={M. {Langhammer} and B. {Pasca}},
booktitle={2017 IEEE 24th Symposium on Computer Arithmetic (ARITH)},
title={Floating Point Tangent Implementation for {FPGAs}},
year={2017},
volume={},
number={},
pages={64-65},
keywords={digital signal processing chips;field programmable gate arrays;fixed point arithmetic;floating point arithmetic;reconfigurable architectures;floating point tangent function;FPGAs;hard floating point DSP blocks;HFP DSP;IEEE-754 single-precision format;OpenCL;generic polynomial approximation methods;resource utilization spectrum;classical CORDIC-based implementations;Intel DSP Builder Advanced Blockset;Field programmable gate arrays;Digital signal processing;Table lookup;Digital arithmetic;Approximation methods;Resource management},
doi={10.1109/ARITH.2017.25},
ISSN={1063-6889},
month={July},
}

Matei Istoan and Bogdan Pasca
Flexible Fixed-Point Function Generation for FPGAs
2017 IEEE 24th Symposium on Computer Arithmetic (ARITH)
London, UK
[bibtex] [pdf]

@INPROCEEDINGS{IstoanPasca2017:ARITH, 
  booktitle={2017 {IEEE} 24th {S}ymposium on {C}omputer {A}rithmetic {(ARITH)}},
  title={Flexible Fixed-Point Function Generation for {FPGAs}},
  year={2017},
  volume={},
  number={},
  pages={123-130},
  keywords={field programmable gate arrays;fixed point arithmetic;flexible fixed-point function generation;FPGAs;convolutional neural networks;computer vision;communication systems;second order Taylor implementation;cubic convergence;Halley method;Field programmable gate arrays;Memory management;Generators;Digital signal processing;Kernel;Signal generators;fixed-point;generator;arithmetic;FPGA;reciprocal;sqrt;reciprocal sqrt},
  doi={10.1109/ARITH.2017.31},
  ISSN={1063-6889},
  month={July},
}

Patrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca and Mark Jervis
Model-based hardware design based on compatible sets of isomorphic subgraphs
2017 International Conference on Field Programmable Technology (ICFPT)
Melbourne, VIC, Australia
[bibtex] [pdf]

@INPROCEEDINGS{SittelEtAl2017:FPT,
  author={P. {Sittel} and K. {Möller} and M. {Kumm} and P. {Zipf} and B. {Pasca} and M. {Jervis}},
  booktitle={2017 {I}nternational {C}onference on {F}ield {P}rogrammable {T}echnology {(ICFPT)}},
  title={Model-based hardware design based on compatible sets of isomorphic subgraphs},
  year={2017},
  volume={},
  number={},
  pages={199-202},
  keywords={field programmable gate arrays;integrated circuit modelling;logic design;compatible sets;isomorphic subgraphs;hardware applications;industrial context;throughput figures;folded circuits;FPGA implementations;automatic combination;pipelined primitive operations;design space exploration;model-based hardware design process;Switches;Resource management;Mathematical model;Hardware;Throughput;Algorithm design and analysis;Integrated circuit modeling},
  doi={10.1109/FPT.2017.8280140},
  ISSN={null},
  month={Dec},
}

Martin Langhammer and Bogdan Pasca
Single Precision Natural Logarithm Architecture for Hard Floating-Point and DSP-Enabled FPGAs
2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH)
Santa Clara, CA, USA
[bibtex] [pdf]

@inproceedings{LanghammerPasca2016:ARITH,
  author = {Langhammer, Martin and Pasca, Bogdan},
  booktitle={2016 {IEEE} 23nd {S}ymposium on {C}omputer {A}rithmetic {(ARITH)}},
  title={Single Precision Natural Logarithm Architecture for Hard Floating-Point and {DSP}-Enabled {FPGAs}},
  year={2016},
  volume={},
  number={},
  pages={164-171},
  keywords={digital signal processing chips;error analysis;field programmable gate arrays;floating point arithmetic;functions;single precision natural logarithm architecture;hard floating-point;DSP-enabled FPGAs;floating point elementary functions;Altera Arria~10 DSP block architecture;datacenter;comprehensive error analysis;hard FP blocks;HFP blocks;flexibility;connectivity;highly accurate single precision IEEE754 function;OpenCL conformant;embedded structures;logic resources;FPGA routing architectures;log x function latency;Field programmable gate arrays;Digital signal processing;Computer architecture;Pipelines;Registers;Performance evaluation;Hardware;natural logarithm;floating-point;FPGA;FP DSP Block;Arria 10},
  doi={10.1109/ARITH.2016.20},
  ISSN={1063-6889},
  month={July},
}

Martin Langhammer and Bogdan Pasca
Floating-Point DSP Block Architecture for FPGAs
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
[bibtex] [pdf]

@inproceedings{LanghammerPasca2015:FPGA,
 author = {Langhammer, Martin and Pasca, Bogdan},
 title = {Floating-Point DSP Block Architecture for FPGAs},
 booktitle = {Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
 series = {FPGA '15},
 year = {2015},
 isbn = {978-1-4503-3315-3},
 location = {Monterey, California, USA},
 pages = {117--125},
 numpages = {9},
 url = {http://doi.acm.org/10.1145/2684746.2689071},
 doi = {10.1145/2684746.2689071},
 acmid = {2689071},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {altera, arria10, dsp, floating-point, fpga, single-precision},
}

Deshanand P. Singh and Bogdan Pasca and Tomasz S. Czajkowski
High-Level Design Tools for Floating Point FPGAs
Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015
[bibtex] [pdf]

@inproceedings{SinghPC15,
  author    = {Deshanand P. Singh and Bogdan Pasca and Tomasz S. Czajkowski},
  title     = {High-Level Design Tools for Floating Point FPGAs},
  booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
               Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
  pages     = {9--12},
  year      = {2015},
  crossref  = {DBLP:conf/fpga/2015},
  url       = {http://doi.acm.org/10.1145/2684746.2689079},
  doi       = {10.1145/2684746.2689079},
  timestamp = {Tue, 24 Feb 2015 08:57:03 +0100},
  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/fpga/SinghPC15},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}

Bogdan Pasca
Low-cost multiplier-based FPU for embedded processing on FPGA
Field Programmable Logic and Applications (FPL), 2014 24th International Conference on
[bibtex] [pdf]

@INPROCEEDINGS{Pasca2014:FPL, 
author={B. Pasca}, 
booktitle={Field Programmable Logic and Applications (FPL), 2014 24th International Conference on}, 
title={Low-cost multiplier-based {FPU} for embedded processing on {FPGA}}, 
year={2014}, 
pages={1-4}, 
keywords={field programmable gate arrays;floating point arithmetic;microprocessor chips;multiplying circuits;reduced instruction set computing;FPU;RISC microprocessor;automatic data range handling;embedded processing;fixed point implementations;floating point solutions;floating-point solutions;industrial applications;low-cost floating-point unit;low-cost multiplier;multiplier-based FPGA;Accuracy;Approximation methods;Computer architecture;Field programmable gate arrays;Kernel;Libraries;Registers}, 
doi={10.1109/FPL.2014.6927407}, 
month={Sept}
}

Adrian J. Chung, Kathryn Cobden, Mark Jervis, Martin Langhammer, Bogdan Pasca
Tools and Techniques for Efficient High-Level System Design on FPGAs
First International Workshop on FPGAs for Software Programmers (FSP 2014)
[bibtex] [pdf]

@article{DBLP:journals/corr/ChungCJLP14,
  author    = {Adrian J. Chung and
               Kathryn Cobden and
               Mark Jervis and
               Martin Langhammer and
               Bogdan Pasca},
  title     = {Tools and Techniques for Efficient High-Level System Design on FPGAs},
  journal   = {CoRR},
  volume    = {abs/1408.4797},
  year      = {2014},
  url       = {http://arxiv.org/abs/1408.4797},
  timestamp = {Fri, 12 Sep 2014 12:44:21 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/corr/ChungCJLP14},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}

Martin Langhammer and Bogdan Pasca
Efficient Floating-Point Polynomial Evaluation on FPGAs
Field Programmable Logic and Applications (FPL), 2013 23nd International Conference on
[bibtex] [pdf]

@inproceedings{LanghammerPasca2013:FPL,
  author={M. {Langhammer} and B. {Pasca}},
  booktitle={2013 23rd {I}nternational {C}onference on {F}ield {P}rogrammable {L}ogic and {A}pplications},
  title={Efficient floating-point polynomial evaluation on {FPGAs}},
  year={2013},
  volume={},
  number={},
  pages={1-6},
  keywords={adders;field programmable gate arrays;floating point arithmetic;polynomial approximation;floating-point polynomial evaluation scheme;FPGA;floating-point coefficients;rational polynomial approximation;floating-point arithmetic;floating-point adders;Horner scheme;fused evaluation operator;alignment shifters;Polynomials;Approximation methods;Digital signal processing;Field programmable gate arrays;Decoding;Approximation algorithms;Standards},
  doi={10.1109/FPL.2013.6645530},
  ISSN={1946-1488},
  month={Sep.},
}

Martin Langhammer and Bogdan Pasca
Elementary Function Implementation with Optimized Sub Range Polynomial Evaluation
Field Programmable Custom Computing Machines 2013 (FCCM'13), Seattle, US
[bibtex] [pdf]

@inproceedings{LanghammerPasca2013:FCCM,
  author    = {Martin Langhammer and Bogdan Pasca},
  title     = {Elementary Function Implementation with Optimized Sub Range Polynomial Evaluation},
  booktitle = {2013 {IEEE} 21st Annual {I}nternational {S}ymposium on {F}ield-{P}rogrammable {C}ustom {C}omputing {M}achines},
  year      = {2013},
  pages     = {202-205},
  ee        = {http://doi.ieeecomputersociety.org/10.1109/FCCM.2013.30},
  crossref  = {DBLP:conf/fccm/2013},
  doi={10.1109/FCCM.2013.30}, 
}

Martin Langhammer and Bogdan Pasca
Faithful Single-Precision Floating-Point Tangent for FPGAs
Field Programmable Gate Arrays 2013 (FPGA'13), Monterey, US
[bibtex] [pdf]

@inproceedings{LanghammerPasca2013:FPGA,
  author = {Langhammer, Martin and Pasca, Bogdan},
  title = {Faithful Single-precision Floating-point Tangent for {FPGAs}},
  booktitle = {{P}roceedings of the {ACM/SIGDA} {I}nternational {S}ymposium on {F}ield {P}rogrammable {G}ate {A}rrays},
  series = {{FPGA}'13},
  year = {2013},
  isbn = {978-1-4503-1887-7},
  location = {Monterey, California, USA},
  pages = {39--42},
  numpages = {4},
  url = {http://doi.acm.org/10.1145/2435264.2435274},
  doi = {10.1145/2435264.2435274},
  acmid = {2435274},
  publisher = {ACM},
  address = {New York, NY, USA},
  keywords = {floating-point, fpga, single-precision, tangent},
}

Florent de Dinechin and Bogdan Pasca
High-Performance Computing using FPGAs, chapter Reconfiguring Arithmetic
Springer, 2012
[bibtex] [pdf]

@Inbook{deDinechin2013,
  author={de Dinechin, Florent and Pasca, Bogdan},
  editor={Vanderbauwhede, Wim and Benkrid, Khaled},
  title={Reconfigurable Arithmetic for High-Performance Computing},
  bookTitle={High-Performance Computing Using FPGAs},
  year={2013},
  publisher={Springer New York},
  address={New York, NY},
  pages={631--663},
  isbn={978-1-4614-1791-0},
  doi={10.1007/978-1-4614-1791-0_21},
  url={https://doi.org/10.1007/978-1-4614-1791-0_21}
}

Florent de Dinechin, Pedro Echeverría, Marisa López-Vallejo, and Bogdan Pasca
Floating-point exponentiation units for reconfigurable computing
ACM Transactions on Reconfigurable Technology and Systems, 2012
[bibtex] [pdf]

@article{DinechinEtAl-2012-power,
  author = {de Dinechin, Florent and Pedro Echeverr\'{i}a  and L\'opez-Vallejo, Marisa and  Bogdan Pasca},
  title = {Floating-Point Exponentiation Units for Reconfigurable Computing},
  journal = {ACM Transactions on Reconfigurable Technology and Systems},
  issue_date = {May 2013},
  volume = {6},
  number = {1},
  month = may,
  year = {2013},
  issn = {1936-7406},
  pages = {4:1--4:15},
  articleno = {4},
  numpages = {15},
  url = {http://doi.acm.org/10.1145/2457443.2457447},
  doi = {10.1145/2457443.2457447},
  acmid = {2457447},
  publisher = {ACM},
  address = {New York, NY, USA},
  keywords = {Reconfigurable Computing, exponentiation unit, floating-point, power function},
}

Christophe Alias, Bogdan Pasca, Alexandru Plesco
FPGA-specific synthesis of loop-nests with pipelined computational cores
Microprocessors & Microsystems, Volume 36 Issue 8, November, 2012, Pages 606-619
[bibtex] [pdf]

@article{AliasPascaPlesco2012:Microproc,
  author = {Alias, Christophe and Pasca, Bogdan and Plesco, Alexandru},
  title = {FPGA-specific synthesis of loop-nests with pipelined computational cores},
  journal = {Microprocessors and Microsystems},
  issue_date = {November, 2012},
  volume = {36},
  number = {8},
  month = nov,
  year = {2012},
  issn = {0141-9331},
  pages = {606--619},
  numpages = {14},
  url = {http://dx.doi.org/10.1016/j.micpro.2012.06.009},
  doi = {10.1016/j.micpro.2012.06.009},
  acmid = {2397465},
  publisher = {Elsevier Science Publishers B. V.},
  address = {Amsterdam, The Netherlands, The Netherlands},
  keywords = {Data-reuse, FPGA, Floating-point, High-level synthesis, Kernel accuracy, 
  Parallelization, Pipelined arithmetic operators, Polyhedral compilation},
}

Bogdan Pasca
Correctly rounded floating-point division for DSP-enabled FPGAs
Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
29-31 Aug. 2012, Oslo, Norway
Won the Michal Servit Award
[bibtex] [pdf]

@inproceedings{Pasca2012:FPL,
  author = {Bogdan Pasca},
  title = {Correctly rounded floating-point division for {DSP}-enabled {FPGA}s},
  booktitle = {22nd {I}nternational {C}onference on {F}ield {P}rogrammable {L}ogic and {A}pplications ({FPL})},
  pages = {249--254},
  year = {2012},
  month={Aug},
  keywords={field programmable gate arrays;rounded floating-point division;DSP-enabled FPGA design;multiplier-based architectures;Altera FPGA;DSP blocks;Altera DSP builder advanced framework;Polynomials;Approximation error},
  doi={10.1109/FPL.2012.6339189},
  ISSN={1946-1488},
}

Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, Alexandru Plesco
An FPGA architecture for solving the Table Maker’s Dilemma
22nd IEEE International Conference on Application-specific Systems, Architectures and Processors
Santa Monica, California, USA, September 11-14, 2011
Won the Best Paper Award
[bibtex] [pdf]

@inproceedings{DinechinMullerPascaPlesco2011:ASAP,
  author = {de Dinechin, Florent and Muller, Jean-Michel and Pasca, Bogdan and Plesco, Alexandru},
  title = {An {FPGA} architecture for solving the {T}able {M}aker's {D}ilemma},
  booktitle = {{ASAP} 2011 - 22nd {IEEE} {I}nternational {C}onference on {A}pplication-specific {S}ystems, {A}rchitectures and {P}rocessors},
  pages={187-194}, 
  keywords={field programmable gate arrays;floating point arithmetic;FPGA architecture;table maker dilemma;floating point format;Field programmable gate arrays;Radiation detectors;Polynomials;Computer architecture;Adders;Accuracy;Approximation methods;table maker's dilemma;floating-point arithmetic;correct rounding;elementary functions;FPGA},
  doi={10.1109/ASAP.2011.6043267},
  ISSN={2160-0511},
  month={Sep.},
  year = {2011},
}

Christophe Alias, Bogdan Pasca, Alexandru Plesco
Automatic Generation of FPGA-Specific Pipelined Accelerators
7th International Symposium on Applied Reconfigurable Computing
23-25 March 2011, Belfast, United Kingdom
[bibtex] [pdf]

@preceedings{AliasPascaPlesco2011:ARC,
  author = {Alias, Christophe and Pasca, Bogdan and Plesco, Alexandru},
  title  = {Automatic Generation of {FPGA}-Specific Pipelined Accelerators},
  booktitle={{R}econfigurable {C}omputing: {A}rchitectures, {T}ools and {A}pplications - {ARC} 2011},
  isbn={978-3-642-19475-7}
  pages={53--66},
  year={2011},
  publisher={Springer Berlin Heidelberg},
  editor={Koch, Andreas and Krishnamurthy, Ram and McAllister, John and Woods, Roger and El-Ghazawi, Tarek},
  address={Berlin, Heidelberg},
}

Hong Diep Nguyen, Bogdan Pasca, Thomas B. Preußer
FPGA-Specific Arithmetic Optimizations of Short-Latency Adders
Field Programmable Logic and Applications, Crete, Greece, 2011
[bibtex] [pdf]

@inproceedings{NguyenPascaPreusser2011:FPL,
  author = {Nguyen, Hong Diep and Bogdan Pasca and Preu{\ss}er, Thomas B.},
  title = {FPGA-Specific Arithmetic Optimizations of Short-Latency Adders},
  booktitle = {2011 21st {I}nternational {C}onference on {F}ield {P}rogrammable {L}ogic and {A}pplications},
  publisher = {IEEE},
  year = {2011},
  pages={232-237},
  doi={10.1109/FPL.2011.49},
  ISSN={1946-1488},
  month={Sep.}, 
}

Florent de Dinechin, Bogdan Pasca
Designing Custom Arithmetic Data Paths with FloPoCo
IEEE Design and Test, July-August 2011
[bibtex] [pdf]

@article{DinechinPasca2011:DT,
  author={F. {de Dinechin} and B. {Pasca}},
  journal={{IEEE} {D}esign {T}est of {C}omputers},
  title={{D}esigning {C}ustom {A}rithmetic {D}ata {P}aths with {FloPoCo}},
  year={2011},
  volume={28},
  number={4},
  pages={18-27},
  keywords={field programmable gate arrays;floating point arithmetic;logic design;pipeline arithmetic;custom arithmetic data path design;FloPoCo;data-path circuit elements;FPGA-based acceleration;scientific computing;pipelined data-path circuits;numerical functions;Pipeline processing;Field programmable gate arrays;Digital signal processing;Synchronization;Generators;design and test;FloPoCo;core generator;arithmetic circuit;floating-point;pipelining;data path;FPGAs;reconfigurable computing;VHDL;C+;+;framework},
  doi={10.1109/MDT.2011.44},
  ISSN={1558-1918},
  month={July},
}

Florent de Dinechin, Bogdan Pasca
Floating-point exponential functions for DSP-enabled FPGAs
International Conference on Field-Programmable Technology, Beijing, China, 2010
[bibtex] [pdf]

@inproceedings{DinechinPasca2010:FPT,
  author={de Dinechin, Florent and Bogdan Pasca},
  booktitle={2010 {I}nternational {C}onference on {F}ield-{P}rogrammable {T}echnology},
  title={Floating-point exponential functions for {DSP}-enabled {FPGAs}},
  year={2010},
  volume={},
  number={},
  pages={110-117},
  keywords={digital signal processing chips;field programmable gate arrays;polynomial approximation;random-access storage;floating-point exponential functions;DSP-enabled FPGA;embedded memory;single-precision operator;dual-port   memory;Virtex-4;polynomial approximation;blockRAM;open-source FloPoCo framework;Field programmable gate arrays;Computer architecture;Digital signal processing;Polynomials;Approximation methods;Accuracy;Adders},
  doi={10.1109/FPT.2010.5681764},
  ISSN={null},
  month={Dec},
}

Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, Radu Tudoran
Multipliers for Floating-Point Double Precision and Beyond on FPGAs
1st International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2010), Tsukuba, Japan, 2010
Republished in ACM SIGARCH Computer Architecture News, Volume 38 Issue 4, September 2010, Pages 73-79
[bibtex] [pdf]

@inproceedings{BanescuDinechinPascaTudoran2010:HEART,
  author = {Sebastian Banescu and de Dinechin, Florent and Bogdan Pasca and Radu Tudoran},
  title = {Multipliers for Floating-Point Double Precision and Beyond on {FPGAs}},
  affiliation = {{ARENAIRE} - {INRIA} {R}h{\^o}ne-{A}lpes / 
  {LIP} {L}aboratoire de l'{I}nformatique du {P}arall{\'e}lisme - {INRIA} - {CNRS} : 
  {UMR}5668 - {U}niversit{\'e} {C}laude {B}ernard - {L}yon {I} - 
  {E}cole {N}ormale {S}up{\'e}rieure de {L}yon - {ENS} {L}yon- 
  {T}echnical {U}niversity of {C}luj-{N}apoca},
  journal = {SIGARCH Comput. Archit. News},
  issue_date = {September 2010},
  volume = {38},
  number = {4},
  month = jan,
  year = {2011},
  issn = {0163-5964},
  pages = {73--79},
  numpages = {7},
  url = {http://doi.acm.org/10.1145/1926367.1926380},
  doi = {10.1145/1926367.1926380},
  acmid = {1926380},
  publisher = {ACM},
  address = {New York, NY, USA},
  keywords = {floating-point, multiplier, quadruple precision, truncated multiplier},
}

Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca
Pipelined FPGA Adders
Field Programmable Logic and Applications, Milano, Italy, 2010
Nominated for FPL Community Award
[bibtex] [pdf]

@inproceedings{DinechinNguyenPasca2010:FPL,
  author = {de Dinechin, Florent and Nguyen, Hong Diep and Bogdan Pasca},
  title = {Pipelined {FPGA} Adders},
  affiliation = {{ARENAIRE} - {INRIA} {R}h{\^o}ne-{A}lpes / 
  {LIP} {L}aboratoire de l'{I}nformatique du {P}arall{\'e}lisme - {INRIA} - {CNRS} : {UMR}5668 - 
  {U}niversit{\'e} {C}laude {B}ernard - {L}yon {I} - 
  {E}cole {N}ormale {S}up{\'e}rieure de {L}yon - {ENS} {L}yon },
  publisher = {{IEEE} },
  booktitle = {2010 {I}nternational {C}onference on {F}ield {P}rogrammable {L}ogic and {A}pplications},
  audience = {internationale},
  x-international-audience = {yes},
  x-proceedings = {yes},
  noday = 31,
  month = aug,
  year = 2010,
  keywords={adders;field programmable gate arrays;pipeline arithmetic;precision engineering;quadprecision floating point integer;elliptic curve cryptography;pipelined large precision FPGA adder architectures;pipelined ripple carry adder;carry select adder;resource estimation models;integer addition;Adders;Field programmable gate arrays;Pipeline processing;Registers;Estimation;Table lookup;addition;pipeline;low-latency;FPGA}, 
  pages={422-427}, 
  doi={10.1109/FPL.2010.87},
  ISSN={1946-1488}, 
}

Florent de Dinechin, Mioara Joldes, Bogdan Pasca, Guillaume Revy
Multiplicative square root algorithms for FPGAs
Field Programmable Logic and Applications, Milano, Italy, 2010
[bibtex] [pdf]

@inproceedings{DinechinJoldesPascaRevy2010:FPL,
  author = {de Dinechin, Florent and Joldes, Mioara and Bogdan Pasca and Guillaume Revy},
  title = {Multiplicative square root algorithms for {FPGA}s},
  affiliation = {{ARENAIRE} - {INRIA} {R}h{\^o}ne-{A}lpes / 
  {LIP} {L}aboratoire de l'{I}nformatique du {P}arall{\'e}lisme - {INRIA} - {CNRS} : {UMR}5668 - 
  {U}niversit{\'e} {C}laude {B}ernard - {L}yon {I} - 
  {E}cole {N}ormale {S}up{\'e}rieure de {L}yon - {ENS} {L}yon },
  publisher = {{IEEE} },
  booktitle = {2010 {I}nternational {C}onference on {F}ield {P}rogrammable {L}ogic and {A}pplications},
  audience = {internationale},
  x-international-audience = {yes},
  x-proceedings = {yes},
  noday = 31,
  month = aug,
  year = 2010,
  pages={574-577}, 
  doi={10.1109/FPL.2010.112},
  ISSN={1946-1488}, 
}

Florent de Dinechin, Mioara Joldes, Bogdan Pasca
Automatic generation of polynomial-based hardware architectures for function evaluation
21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP10), Rennes, France, 2010
[bibtex] [pdf]

@inproceedings{DinechinJoldesPasca2010:ASAP,
  author = {de Dinechin, Florent and Joldes, Mioara and Bogdan Pasca},
  title = {Automatic generation of polynomial-based hardware architectures for function evaluation},
  booktitle = {{ASAP 2010} - 21st {IEEE} International Conference on {A}pplication-specific {S}ystems, {A}rchitectures and {P}rocessors ({ASAP})},
  year = 2010,
  pages={216-222}, 
  address = {Rennes},
  doi={10.1109/ASAP.2010.5540952},
  ISSN={1063-6862}, 
  month = jul
 }

Florent de Dinechin, Mioara Joldes, Bogdan Pasca, Guillaume Revy
Racines carrées multiplicatives sur FPGA
Symposium en Architecture de machines, Toulouse, France, 2009
[bibtex] [pdf]

@inproceedings{DinechinJoldesPascaRevy2009:SYMPA,
  author = {de Dinechin, Florent and Joldes, Mioara and Bogdan Pasca and Guillaume Revy},
  title = {Racines carr{\'e}es  multiplicatives sur {FPGA}},
  booktitle = {{SYMP}osium en Architectures nouvelles de machines ({SYMPA})},
  year = 2009,
  address = {Toulouse},
  pdf = {http://bogdan-pasca.org/resources/publications/RRLIP-2009-19.pdf},
  month = sep
}

Florent de Dinechin and Bogdan Pasca
Large multipliers with fewer DSP blocks
Field Programmable Logic and Applications, Prague, Czech Republic, 2009
[bibtex] [pdf]

@inproceedings{DinechinPasca2009:FPL,
  title = {{L}arge multipliers with fewer {DSP} blocks},
  author = {de Dinechin, Florent and Pasca, Bogdan},
  nokeywords = {{FPGA};reconfigurable computing;integer multiplier;{K}aratsuba-{O}fman},
  affiliation = {{ARENAIRE} - {INRIA} {R}h{\^o}ne-{A}lpes / 
  {LIP} {L}aboratoire de l'{I}nformatique du {P}arall{\'e}lisme - {INRIA} - {CNRS} : {UMR}5668 - 
  {U}niversit{\'e} {C}laude {B}ernard - {L}yon {I} - 
  {E}cole {N}ormale {S}up{\'e}rieure de {L}yon - {ENS} {L}yon },
  publisher = {{IEEE} },
  booktitle={2009 International Conference on Field Programmable Logic and Applications},
  audience = {internationale},
  x-international-audience = {yes},
  x-proceedings = {yes},
  noday = 31,
  month = aug,
  year = 2009,
  pages={250-255},
  doi={10.1109/FPL.2009.5272296},
  ISSN={1946-1488}
}

Florent de Dinechin, Cristian Klein, Bogdan Pasca
Generating high-performance custom floating-point pipelines
Field Programmable Logic and Applications, Prague, Czech Republic, 2009
[bibtex] [pdf]

@inproceedings{DinechinKleinPasca2009:FPL,
  author={F. {de Dinechin} and C. {Klein} and B. {Pasca}},
  booktitle={2009 International Conference on Field Programmable Logic and Applications},
  title={Generating high-performance custom floating-point pipelines},
  affiliation = {{ARENAIRE} - {INRIA} {R}h{\^o}ne-{A}lpes / 
  {LIP} {L}aboratoire de l'{I}nformatique du {P}arall{\'e}lisme - {INRIA} - {CNRS} : {UMR}5668 - 
  {U}niversit{\'e} {C}laude {B}ernard - {L}yon {I} - 
  {E}cole {N}ormale {S}up{\'e}rieure de {L}yon - {ENS} {L}yon},
  year={2009},
  volume={},
  number={},
  pages={59-64},
  keywords={field programmable gate arrays;floating point arithmetic;hardware description languages;logic design;floating-point pipeline;FPGA;open-source architecture generator;VHDL;frequency-directed pipeline;automatic test-bench     generation;Pipelines;Field programmable gate arrays;Open source software;Computer architecture;Frequency synthesizers;Automatic testing;Detectors;Digital signal processing;Logic;Delay},
  doi={10.1109/FPL.2009.5272553},
  ISSN={1946-1488},
  month={Aug}
}

Florent De Dinechin, Bogdan Pasca, Octavian Cret and Radu Tudoran
An FPGA-specific Approach to Floating-Point Accumulation and Sum-of-Products
International Conference on Field-Programmable Technology, Taipei, Taiwan, 2008
[bibtex] [pdf]

@inproceedings{DinechinPascaCret2008:FPT,
  author={F. {de Dinechin} and B. {Pasca} and O. {Cret} and R. {Tudoran}},
  booktitle={2008 International Conference on Field-Programmable Technology},
  title={An {FPGA}-specific approach to floating-point accumulation and sum-of-products},
  affiliation = {{ARENAIRE} - {INRIA} {R}h{\^o}ne-{A}lpes / 
  {LIP} {L}aboratoire de l'{I}nformatique du {P}arall{\'e}lisme - {INRIA} - {CNRS} : {UMR}5668 - 
  {U}niversit{\'e} {C}laude {B}ernard - {L}yon {I} - 
  {E}cole {N}ormale {S}up{\'e}rieure de {L}yon - {ENS} {L}yon - 
  {T}echnical {U}niversity of {C}luj-{N}apoca},
  year={2008},
  volume={},
  number={},
  pages={33-40},
  keywords={field programmable gate arrays;floating point arithmetic;microprocessor chips;FPGA-specific approach;floating-point accumulation;sum-of-product;design application-specific floating-point operator;ad-hoc accumulator;floating-point multiplier;FloPoCo generator;processor floating point unit;graphic processing unit;},
  doi={10.1109/FPT.2008.4762363},
  month={Dec}
}

PhD Thesis

High-performance floating-point computing on reconfigurable circuits
École Normale Supèrieure de Lyon 2011
[bibtex] [pdf]

@PhdThesis{PascaPHD:2011,
  author       = {Bogdan Pasca},
  title        = {High-performance floating-point computing on reconfigurable circuits},
  school       = {\'Ecole Normale Sup\'erieure de Lyon},
  address      = {Lyon, France},
  month        = sep,
  year         = 2011,
  url          = {http://tel.archives-ouvertes.fr/docs/00/65/41/21/PDF/Bogdan_PASCA-Calcul_flottant_haute_performance_sur_circuits_reconfigurables_2011.pdf}
}

Master Thesis

Customizing floating-point operators for linear algebra acceleration on FPGAs
École Normale Supèrieure de Lyon 2008
[bibtex] [pdf]

@MASTERSTHESIS{Pasca2008:MASTER,
    author = {Pasca, Bogdan},
     month = jun,
     title = {Customizing floating-point operators for linear algebra acceleration on FPGAs},
      year = {2008},
    school = {{\'{E}}cole Normale Sup{\'{e}}rieure de Lyon},
       url = {http://perso.ens-lyon.fr/bogdan.pasca/resources/publications/Master2 Report - Bogdan Pasca 2008.pdf}
}

Talks

Faithful Single-Precision Floating-Point Tangent for FPGAs
Field Programmable Gate Arrays 2013 (FPGA'13) Monterey, US, Feb 12 2013 [PDF]
Correctly rounded floating-point division for DSP-enabled FPGAs
Field Programmable Logic and Applications (FPL), 29-31 Aug. 2012, Oslo, Norway [PDF]
FPGA-specific arithmetic pipeline design using FloPoCo
CARAMEL workgroup, Nancy, Feb 17 2011 [PDF]
FPGA Multipliers
4es Rencontre Arithmétique, Informatique et Mathématique (RAIM11), Perpignan, France, 2011 [PDF]
Pipelined FPGA adders
Field Programmable Logic and Applications, Milano, Italy, Aug. 31st - Sep. 2nd, 2010 [PDF]
Automatic generation of polynomial-based hardware architectures for function evaluation
Application-specific Systems, Architectures and Processors (ASAP10) [PDF]
Multipliers for Floating-Point Double Precision and Beyond on FPGAs
International Workshop on Higly-Efficient Accelerators and Reconfigurable Technologies [PDF]
Automatic generation of polynomial-based hardware architectures for function evaluation
EvaFlo Reunion 20-21 May 2010, Perpignan - Canet [PDF]
Pipelined FPGA adders
Arenaire workgroup Janary 21, 2010, Lyon [PDF]
Multipliers and Square Root for FloPoCo
EvaFlo Reunion 22-23 September 2009, Lyon [PDF]
Large multipliers with fewer DSP blocks
Field Programmable Logic and Applications, Prague, Czech Republic, 2009 [PDF]
An FPGA-specific Approach to Floating-Point Accumulation and Sum-of-Products
International Conference on Field-Programmable Technology, Taipei, Taiwan, 2008 [PDF]
Bogdan Pasca et Cristian Klein
FloPoCo, un générateur de coeurs arithmétiques pour FPGA
2eme Rencontre Arithmétique, Informatique et Mathématique (RAIM08), Lille, France, 2008 [PDF]

Posters

Martin Langhammer and Bogdan Pasca
Faithful Single-Precision Floating-Point Tangent for FPGAs
Field Programmable Gate Arrays, Monterey, US, 2013 [PDF]
Bogdan Pasca and Florent de Dinechin
FloPoCo - an arithmetic core generator for FPGAs
Architectures des systèmes matériels enfouis et méthodes de conception associées, Pleumeur-Bodou, France, 2009 [PDF]

Hardware and software realizations

FloPoCo
Senior developer in the FloPoCo project, a generator of arithmetic cores for FPGAs.

Updated: